P1149.4-Problem or Solution for Mixed-Signal IC Design?

Almost any new circuitry which falls under the category Design For Testability (DFT) is perceived by designers as a problem to be endured to make someone else’s job easier, i.e. that of the manufacturing engineer. After all, no net benefit is gained by simply transferring problems from manufacturing into design. Even if there is a net benefit, the designer may not derive a benefit. For a new DFT method to get accepted it must make the designer’s job easier or faster. For example, scan paths were only well accepted after IC designers found them to be invaluable for debugging ICs and software that used the ICs, and for automating test pattern creation. The issue of whether the proposed P1149.4 Standard for a Mixed-Signal Test Bus will be a net benefit to board level design and test seems to be more or less settled: for the extremely dense circuit boards which will be commonplace in five years, and in today’s multi-chip modules, P1149.4 offers a solution where no other exists. P1149.4 was aimed at solving test issues for these mixedsignal boards. For boards which do not have test access issues, P1149.4 may not be worth its costs. So the key question about the proposed P1149.4 Standard is whether it will be a net benefit for IC designers, without considering the system-level benefits.